Particularly for mobile devices, power consumption is a major issue. Memory is one component for which a reduction in power consumption is desired. Modern low power memory designs typically include multiple voltage domains, which include a low voltage domain for wordline decoding logic and a high voltage domain for the memory array and read and write circuits. Specifically, due to relatively high minimum voltage requirements, the memory array must use a higher supply voltage than what is needed for the wordline decoding logic. As a result of implementing the wordline decoding logic in the low voltage domain, power consumption is reduced.
One issue that arises in multi-voltage domain memory is that device variations in the low voltage domain significantly impact the high voltage domain. More specifically, because devices typically operate much faster in the high voltage domain than in the low voltage domain, timing glitches that result from device variation in the low voltage domain translate to large timing glitches in the high voltage domain. For example, a 50 pico second glitch in the low voltage domain may be considered a relatively small timing glitch, but the same 50 pico second timing glitch in the high voltage domain may be considered a large timing glitch. As a result of device variation and the corresponding timing glitch, control signals for multi-voltage domain memory (e.g., wordlines, pre-charge control signal, sense amplifier enable signal, etc.) may not maintain a stable relationship between one another, which in turn may cause the multi-voltage domain memory to fail. As such, there is a need for systems and methods for maintaining a stable relationship between control signals in multi-voltage domain memory.